1. Field of the Invention
This invention relates to a MOS current switching circuit comprising a plurality of MOS field effect transistors (FETs), particularly to a current switching circuit to be used for switching an analog current with high precision in a monolithic integrated circuit (hereafter referred to monolithic IC) of complementary MOS transistors (hereafter referred to as CMOS) and the like.
2. Description of the Related Art
A prior art current switching circuit has been disclosed in Japanese Patent Laid-Open Publication Nos. 56-107638 and 59-186420.
An arrangement of the prior art CMOS current switching IC is described with reference to FIG. 4.
The arrangement of the current switching circuit comprises a first power supply voltage Vdd, a second power voltage supply Vss; a switching circuit 20 composed of a NAND gate 25 comprising P-channel FETs 25a, 25b and N-channel FETs 25c, 25d, power supply terminals 26, 27 for receiving voltage from the first and second power supply voltages Vdd and Vss, an input current terminal 21 for receiving current from a current source 10 (described later), an output current terminal 23 for supplying the current, and a control terminal 22 for receiving a control signal from a control signal generator (not shown); the current source 10 is composed of a p-channel FET 10a and connected to the power supply voltage Vdd and the input terminal 21. To the gate of the p-channel FET 10a is applied a bias voltage by a bias voltage terminal Vb.
With the arrangement set forth above, an output current from the current source 10 can be supplied or not supplied via the input current terminal 21 to the output current terminal 23 in response to a control signal in high level (hereafter referred to as H level control signal) or in a low level (hereafter referred to as L level control signal). Provided that the H level control signal is applied to the control terminal 22, the current is supplied from the input current terminal 21 to a gate electrode of the FET 24 whereby the NAND gate 25 operates as an inverting amplifier having an input terminal thereof at the side of the input current terminal 21 and an output terminal thereof. As a result, the FET 24 is conductive since a feedback bias signal from the NAND gate 25 is applied to the gate electrode of the FET 24 whereby the FET 24 is feedback biased and an output current is supplied from the output terminal 23. On the contrary, provided that the control signal is L level at the control terminal 22, the output signal of the NAND gate 25 becomes H level to render the FET 24 to be non-conductive, hence no current is supplied to the output terminal 23.
FIG. 6 shows an arrangement of another prior art current switching circuit for providing complementary output currents.
The arrangement of the current switching circuit 20A comprises an input current terminal 21 for receiving a current from a current source 10, a P-channel FET 24-1, a NAND gate 25-1 which are connected with each other in series between the input current terminal 21 and an output current terminal 23-1, a P-channel FET 24-2, a NAND gate 25-2 which are connected with each other in series between the input current terminal 21 and an output current terminal 23-2, a control terminal 22 for receiving a control signal from a control signal generator (not shown) and supplying the control signal to an inverter 28 and the NAND gate 25-2, the inverter 28 for inverting the control signal received from the control terminal 22 and supplying the inverted control signal to the NAND gate 25-1. The NAND gates 25-1, 25-2 provides complementary output H level and L level voltage to permit the FETs 24-2, 24-1 to be in complementary conductive or nonconductive state. As a result, output current is supplied from one of the output current terminals 23-1 or 23-2.
The prior art current switching circuits as illustrated in FIGS. 4 and 6 have features in that firstly an output impedance of the current supplied from the output current terminals 23, 23-1, 23-2 is high, secondly, the arrangement of these current switching circuits are adapted for the monolithic IC, and thirdly, a bias voltage for switching is unnecessitated to be supplied from the outside.
However, there are following problems in the prior art current switching circuit.
(1) One NAND gate 25 has a switching function as well as an inverting amplification function. However, due to characteristic of the NAND gate 25, an input threshold voltage Vt is varied at the time of switching operation (transition operation), hence the output current is likely to be varied.
More in detail, when the FET 24 as a curent switch is switched to be conductive or nonconductive, the NAND gate 25 having an inverting amplification function and providing the feedback bias voltage is switched from a conductive state to a nonconductive state or from the nonconductive state to the conductive state so that the input current terminal 21 connected to the input side of the NAND gate 25 is varied at the time when the FET 24 is switched to the conductive state or the nonconductive state whereby a noise is produced in the output current supplied from the output current terminal 23. That is, when the control signal applied to the control terminal 22 is switched from L level to H level, the voltage at the input side of the NAND gate, namely at the side of the input current terminal 21 is switched to the H level from the L level and the FET 24 is switched to the nonconductive state from the conductive state. At this time, there appeared a period when a threshold voltage at the output side of the NAND gate 25 is higher than that of a normal state until the threshold voltage at the output side of the NAND gate 25 reaches the threshold voltage at the normal state. As a result, the threshold voltage at the output side of the NAND gate 25 is higher than that of a normal state so that the voltage at the side of the gate electrode of the FET 24 is lower than that of the normal state. Due to the threshold voltage being lower than that of the normal state, a resistance between the source and the drain of the P-channel FET 24 is lower than that of the normal state. At that period, a current value supplied from the current source is greater than the predetermined current value. Accordingly, as shown in FIG. 5 (b) representing a current wave, the noise is produced at a leading edge so that a value of output current is varied, which results in a settling time for stabilizing the output current.
(2) According to the arrangement of the current switching circuit in FIG. 6, as same as in the arrangement of the prior art current switching circuit as shown in FIG. 4, when the control signal from the control terminal 22 is switched to the H level from the L level, the input terminal of the NAND gate 25-2 at the side of control terminal 22 is switched to the H level from the L level while the input terminal of the NAND gate 25-1 is switched to the L level from the H level whereby the FET 24-1 is switched to the nonconductive state from the conductive state while the FET 24-2 is switched to the conductive state from the nonconductive state. At this period, the noise is produced at the leading edge of the output current supplied from the output terminal 23-2 as illustrated in FIG. 5(b) whereby the output current is varied.
The NAND gates 25-1, 25-2 employed in the prior art current switching circuit in FIG. 6 provides complementary output signals. Namely, two NAND gates 25-1, 1, 25-2 are employed to provide the complementary output signals. However, it is difficult to permit the threshold voltage Vt of the NAND gates 25-1, 25-2 to be completely in the same level due to variations produced in manufacturing the NAND gates such as improper masking, variation of dispersion of impurity, and variation of thickness of oxide film. As a result, the NAND gates 25-1, 1, 25-2 have normally different characteristics whereby everytime the FETs 24-1, 24-2 are switched to conductive state or nonconductive state, the current value is varied. As a result, it is impossible to obtain complementary output currents of the same value.